Research

My CV is available, here

Journal Link to heading

1. Kojima Takuya , Morita Masaki , Takase Hideki , Nakamura Hiroshi ,
   “An Open-Source Framework for Efficient Side-Channel Analysis on Cryptographic Implementations”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2025.

International Conferences | Peer Reviewed Link to heading

1. Morita Masaki , Kojima Takuya , Ishii Haruto , Takase Hideki , Nakamura Hiroshi ,
   “A Data Compression Method for DL-SCAs using Denoising Autoencoders”, IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 28), Tokyo, Japan, 2025. (Poster)
2. Morita Masaki , Kojima Takuya , Ishii Haruto , Takase Hideki , Nakamura Hiroshi ,
   “A Denoising Preprocess Method for Side-Channel Attacks Using Autoencoders”, IEEE International Symposium on Hardware Oriented Security and Trust (HOST), San Jose, The United States of America, 2025. (Presentation and Demonstration)

Japan Domestic Conferences | Non-Peer Reviewed Link to heading

1. Morita Masaki , Kojima Takuya , Ishii Haruto , Takase Hideki , Nakamura Hiroshi ,
   “Optimizing Deep Learning Based Side-Channel Attacks Methods by Preprocessing Based on Autoencoder”, Technical Report (HWS), Naha, Okinawa, 2025. (Oral Presentation)
2. Morita Masaki , Kojima Takuya , Takase Hideki , Nakamura Hiroshi ,
   “An Autoencoder-based Compression for a faster DL-SCA”, Cross-Disciplinary workshop on computing Systems, Infrastructures, and programming(xSIG), Takamatsu, Kagawa, 2025. (Poster)

Awards and Honors Link to heading

• Featured Poster Award COOL Chips 28, April 2025